2025-09-06 13:22:24 +08:00
2025-09-06 13:22:24 +08:00
2025-09-06 13:22:24 +08:00
2025-09-06 13:22:24 +08:00
2025-09-06 13:22:24 +08:00

docker run -it --rm -v /Users/oushiha/chip_design:/workspace swangnice/verilog-toolbox:latest

docker run -it --rm -e -e DISPLAY=host.docker.internal:0 -v /Users/oushiha/Desktop/server_buffer/chip_design/rv32i:/workspace swangnice/verilog-toolbox:latest

Description
Chips Design in Verilog/SV
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